With two new research papers and an updated quantum roadmap, IBM® lays out a clear, rigorous, comprehensive framework for realizing a large-scale, fault-tolerant quantum computer by 2029.

By Ryan Mandelbaum, Jay Gambetta, Jerry Chow, Tushar Mittal, Theodore J. Yoder, Andrew Cross, Matthias Steffen, IBM Corporation

 Below, we’ll lay out our architecture in more detail and explain how it meets these criteria. But before we do that, let’s briefly review how we detect and correct errors that arise in quantum computers.

Correcting errorsThe information of a logical qubit is encoded across many physical qubits to make it more resilient against errors.

Quantum error correction is the name for a family of techniques where we encode quantum information into physical qubits to protect them against errors. We do something similar in conventional computing. If we have three physical transistors and want to encode one binary digit's worth of information into them, then we could represent 0 as 000, and we could represent 1 as 111. We can define correction as majority voting — so even if one transistor errors, the encoded data isn’t corrupted. Let’s call 000 and 111 our three physical bits, and call the 0 and 1 they represent our logical bits.

Our goal is to do something similar in quantum computing — construct logical quantum bits, or qubits, from physical qubits. A physical qubit is a unit of well-isolated quantum computing hardware capable of being programmed and coupled to more than one other qubit in a controllable manner. A logical qubit is a qubit’s worth of encoded information that can be made from one or more physical qubits, depending on the quantum error correction code.

The information of a logical qubit is encoded across many physical qubits to make it more resilient against errors.

We denote a quantum code’s parameters by [[n, k, d]] where n is the number of physical data qubits required, k is the resulting number of logical qubits, and d is the distance of the code — how many errors it takes to silently corrupt the data encoded on the logical qubit (i.e., how many errors it takes to change an error-free encoded state to another encoded state that appears completely error-free). In a classical analog, you’d say the above code (0 = 000, 1 = 111) is a [3, 1, 3] code (note the single bracket for a classical code). An error correction code can correct up to (d-1)/2 errors and detect up to d-1 errors.

Just like classical computing, we can represent 0 and 1 as specific quantum states that incorporate multiple qubits. You might encode |00⟩ as |0000⟩+|1111⟩, |01⟩ as |1100⟩+|0011⟩, |10⟩ as |1010⟩+|0101⟩ and |11⟩ as |1001⟩+|0110⟩, for example. Then, we can monitor these qubits by regularly running error syndrome extraction circuits, which detect evidence of errors — for example, measuring an output with an odd number of 1s in the case described above would be an obvious error. Together, these make up what we call the quantum memory.

But you need more than a memory to compute. Quantum computing requires a universal gate set, or a set of logic gates to which every quantum computation can be reduced. Our universal gate set begins with a group of familiar gates called Clifford gates, which must run on the encoded information quickly and with limited overhead. It also requires at least one non-Clifford gate, such as the T gate, which is harder to realize. We apply T gates by creating special states called “magic states” on helper qubits, then we entangle these qubits into our circuits with Clifford gates.

We also need to be able to read out the logical qubits — for this, we use a tool called the decoder. This is classical hardware capable of reading the error syndromes, updating our beliefs about errors in real time, and outputting the corrected information. Finally, this whole system must be modular — it must scale to sizes large enough to run meaningful computations.

An architecture for realizing fault-tolerant quantum computing

Our new paper¹ presents an architecture based on years of prior work, which meets these requirements for fault-tolerant quantum computing in a scalable system.

Our fault-tolerant modular architecture is based on the bivariate bicycle code developed by IBM.

Let’s walk through each step of that architecture. In 2024, we introduced a fault-tolerant quantum memory² based on quantum low-density parity check (qLDPC) codes called bivariate bicycle (BB) codes. The [[144,12,12]] gross code encodes 12 logical qubits into 144 data qubits—a gross—along with another 144 syndrome check qubits, for a total of 288 physical qubits. This code corrects errors just as well as the surface code does, but requires 10x fewer qubits to do so.

The gross code developed by IBM encodes 12 logical qubits into 144 data qubits, or a 'gross' of data qubits, along with an additional 144 syndrome check qubits. Achieving this on the 2D surface of a quantum chip requires long-range connections between distant qubits within the chip — connections which follow the symmetry of a 3D torus.

Last year, our team and their collaborators discovered that we could build efficient, fault-tolerant logical processing units (LPUs) for qLDPC codes^{4 , 5}. These LPUs are based on a technique called generalized (lattice) surgery⁶ and have valuable properties: they perform logical measurements using low-weight checks, and do so with very few additional qubits. We can use LPUs together with the symmetries of the qLDPC code to perform logical stabilizer computations, such as Clifford gates, state preparations, and measurements. In our new paper¹, we design efficient LPUs for the gross code and a larger [[288,12,18]] BB code called the two-gross code that corrects more errors. The combined memory and LPU is one type of module in our architecture.

Our team and their collaborators also introduced concepts for universal adapters, which use bridges to interact and move logical quantum information between modules^{4 , 7}. Parts of the adapters can be implemented using the inter-module microwave l-couplers we first demonstrated last year with IBM Quantum Flamingo. Our new paper¹ elaborates on the adapter construction and characterizes a baseline inter-module measurement instruction.

L-couplers enable long-range connections between qubits on separate quantum chips.

Universal computation can be done by augmenting logical stabilizer computations with magic state factories that create, distill, and consume magic states to apply universal gates. Sergey Bravyi and Alexei Kitaev invented the process of magic state distillation in 2004⁸. Our team has made numerous contributions to the development of magic state preparation protocols since then, and in 2024, we published an experimental demonstration⁹ of such a protocol. Our new paper constructs explicit universal fault-tolerant instruction sets using adapters and magic state factory modules, and presents a compilation strategy adapted to the constraints of the bicycle architecture. This enables all of the operations we need for universal quantum computing.

New paper details a modular fault-tolerant architecture with magic state factory.

The last step is an error correcting decoder, which we will introduce in the Starling proof-of-concept slated for 2028. Alongside our architecture paper, we present the first decoder architecture³ that is accurate, fast, flexible, and compact. It can fit on an FPGA or ASIC, classical components that are ubiquitous today. This decoding technique, called Relay-BP, achieves a 5x-10x reduction over other leading decoders, and shows that we do not need to use large amounts of HPC to perform the decoding required for fault-tolerant quantum computations.

Next time: The IBM roadmap to fault-tolerant quantum computing