02
Sat, Nov
2 New Articles

How Do I Know if Two Space Pointers Do Not Address the Same SLS Segment in ILE HLL Programs?

RPG
Typography
  • Smaller Small Medium Big Bigger
  • Default Helvetica Segoe Georgia Times

 

Learn the PowerPC instruction on which this technique is based.

 

In IBM i, a space pointer is used to address bytes within a space. The addressability contained in a space pointer is the Single-Level Store (SLS) virtual address or the process-local Teraspace address stored in the 8-byte address portion. The distinguishing SLS addressing mechanism used by IBM i and its ancestors (AS/400 and System/38) is no doubt one of the cornerstones of the system. From the point of view of storage management, SLS is also the base of the object-based architecture of the system.

 

The huge SLS addressing space is divided into non-overlapping 16 MB segments. All Machine Interface (MI) objects are composed of one or more SLS segments. An associated space (either primary or secondary) of an MI object occupies one SLS segment. For programs running in the SLS storage model, program storage such as automatic storage frames, static storage frames, and heap storage are also composed of SLS segments. In a segmented addressing space, comparing two addresses in different segments to see which one is less or greater is obviously meaningless. So in ILE high-level languages (HLLs), how can we be sure that two space pointers do not address the same SLS segment?

 

The answer to this question might surprise you. In an ILE HLL program, to tell that two space pointers do not address the same SLS segment (I will refer to this condition as "UNEQ" in the remaining part of this article) look for the following:

  1. 1.The two space pointers address different SLS segments.
  2. 2.One of the space pointers addresses the SLS addressing space, while the other one does not (for example, addressing the Teraspace of an MI process or being a null pointer).
  3. 3.One of the space pointers addresses the Teraspace, while the other one does not (for example, addressing the SLS or being a null pointer).

 

You need to test for the following condition:

 

(pointer-A is NOT greater than pointer-B) AND

(pointer-A is NOT less than pointer-B) AND

(pointer-A is NOT equal to pointer-B)

 

Say ptra@ and ptrb@ are two pointer variables used as space pointers within an ILE RPG program. The if statement to tell that ptra@ and ptrb@ do not address the same SLS segments should like the following:

 

if NOT (ptra@ > ptrb@) AND

     NOT (ptra@ < ptrb@) AND

     NOT (ptra@ = ptrb@);

     // ptra@ and ptrb@ do not address the same SLS segment

endif;

 

In IBM i and its ancestors, different types of pointers are the basic data types of the high-level Machine Interface of the system. The type of a pointer defines the capability that you have through it. For example, you can execute a program via a system pointer addressing the program object; however, you cannot access the contents of the program via the system pointer. In ILE HLL programs, a comparison of two pointers for the greater than (GT), less than (LT), or equal to (EQ) conditions are implicitly treated as the comparison of the addressability contained in these space pointers. (RPG pointer variables defined with the PROCPTR keyword are an exception.) In IBM i, the key PowerPC instruction used for the addressability comparisons is the CMPLA instruction (discussed later in this article), which possibly results in one of four mutually exclusive comparison results (negative (LT), positive (GT), equal (EQ), and Summary Overflow (SO)) to indicate the four possible relationships between the addresses (say, addr_a and addr_b):

 

  1. 1.LTaddr_a and addr_b address the same 16 MB segment (range from SID-000000 to SID-FFFFFF). addr_a is less than addr_b. Here, SID refers to the high-order 5 bytes of an 8-byte address, which is also the SLS segment identifier for an SLS address.
  2. 2.GTaddr_a and addr_b address the same 16 MB segment. addr_a is greater than addr_b.
  3. 3.EQaddr_a and addr_b address the same 16 MB segment. addr_a is equal to addr_b.
  4. 4.UNEQaddr_a and addr_b do not address the same 16 MB segment.

 

The following tiny ILE RPG example, cmpla01.rpgle, tests the relationship between the addressability stored in the two input space pointers and returns the comparison result via the 1-byte parameter rtn. The program logic to determine the UNEQ condition is the same as the above-shown RPG code.

 

     d i_main          pr                 extpgm('CMPLA01')

     d     ptra@                         *

     d     ptrb@                         *

     d     rtn                         1a

 

     d i_main         pi

     d     ptra@                         *

     d     ptrb@                        *

     d     rtn                         1a

 

STMT /free

NUM:       select;

16         when ptra@ > ptrb@; // GT

17             rtn = 'G';

18         when ptra@ < ptrb@; // LT

19             rtn = 'L';

20         when ptra@ = ptrb@; // EQ

21             rtn = 'E';

22         other;             // UNEQ

23             rtn = 'U';

24         endsl;

 

26         *inlr = *on;

     /end-free

 

Example programs written in ILE C, ILE CL, and ILE COBOL that implement the same program logic are available as cmpla02.c, cmpla03.clle, and cmpla04.cblle, respectively. ILE RPG program cmpla99.rpgle calls CMPLA01 through CMPLA04 to see whether it can detect the UNEQ condition successfully.

 

     d pgms           ds

     d                               40a     overlay(pgms:1)

     d                                       inz('CMPLA01   +

     d                                       CMPLA02   +

     d                                    CMPLA03   +

     d                                       CMPLA04   ')

     d     pgmarr                     10a     dim(4) overlay(pgms:1)

     d ptra@           s               *

     d ptrb@           s               *

     d rtn            s             1a

     d inx             s             5u 0

     d msg             s             11a

 

     c       cmpplist     plist

     c                   parm                   ptra@

     c                   parm                   ptrb@

     c                    parm                   rtn

 

     c                   exsr     prep_ptr_uneq

     c                   for       inx = 1 to 4

     c                   eval     rtn = *blank

 

     c                   call     pgmarr(inx)   cmpplist

     c                   eval     msg = pgmarr(inx) + rtn

     c       msg           dsply

     c                   endfor

     c

     c                   seton                                       lr

     /free

         begsr prep_ptr_uneq;

               ptra@ = %addr(rtn); // ptra@ addresses the SSF

               ptrb@ = %alloc(1);   // ptrb@ addresses the heap storage

           endsr;

     /end-free

 

Note: Make sure CMPLA99 is compiled with parameter STGMDL(*SGNLVL) on V7R1M0 or later. For a program using the Teraspace storage model, the static storage frame (SSF) and heap storage are all allocated from the Teraspace of the MI process the program is running in.

 

Calling CMPLA99, the output might look like the following:

 

4 > CALL CMPLA99

     DSPLY   CMPLA01   U

     DSPLY   CMPLA02   U

     DSPLY   CMPLA03   U

     DSPLY   CMPLA04   U

 

Now we've proven the method to test for the condition that the addressability contained in two space pointers is not in the same SLS segment. If you are interested with why this technique works, please read on.

Analyze Addressability Comparisons in ILE HLL Programs at the RISC Instruction Level

The following are the PowerPC instructions generated (at V5R4M0) for statement 16, when ptra@ > ptrb@, of ILE RPG program cmpla01.rpgle. (Part of the PowerPC instructions generated for statement 17, 18, and 26 are also included for convenience of illustration.)

 

RISC INSTRUCTIONS (CMPLA01)

Location

Object text

Source statement

Pseudocode/Comments

000570

000574

000578

00057C

000580

000584

000588

00058C

000590

000594

000598

00059C

0005A0

0005A4

0005A8

0005AC

0005B0

0005B4

0005B8

0005BC

0005C0

0005C4

0005C8

0005CC

0005D0

0005D4

0005D8

0005DC

...  

0006D4

E29E0206

7ABA049C

E2DE01F6

7AF8049C

E25A0006

7A79049C

E2980006

7AB6049C

7DB9B080

40EF0020

7B372720

2A370009

40920014

7AD22720

29320009

408A0008

7DB9B040

3B400001

418D0008

3B400000

2E3A0000

41920018

E25E01E6

7A74049C

3B0000C7

9B140000

480000FC

E29E0206

      

3A6000F1

LQ 20,0X200(30),6

SELRI 26,21,0,41

LQ 22,0X1F0(30),6

SELRI 24,23,0,41

LQ 18,0X0(26),6

SELRI 25,19,0,41

LQ 20,0X0(24),6

SELRI 22,21,0,41

CMPLA 3,25,22

BC 7,15,0X20

RLDICL 23,25,4,60

CMPLI 4,1,23,9

BC 4,18,0X14

RLDICL 18,22,4,60

CMPLI 2,1,18,9

BC 4,10,0X8

CMPL 3,1,25,22

ADDI 26,0,1

BC 12,13,0X8

ADDI 26,0,0

CMPI 4,1,26,0

BC 12,18,0X18

LQ 18,0X1E0(30),6

SELRI 20,19,0,41

ADDI 24,0,199

STB 24,0X0(20)

B 0XFC

LQ 20,0X200(30),6

 

ADDI 19,0,241

stmt_16: // when ptra@ > ptrb@;

 

 

 

   // Load ptra@ [1]

   r25 = addr_a // [1.1]

   // Load ptrb@ [2]

   r22 = addr_b

   // Compare addr_a and addr_b using CMPLA [3]

   if NOT SO; then goto check_gt_cnd // [4]

SO: r23 = bits 0-3 of addr_a // [4.SO]

   // Compare r23 with the immediate value 9

   if addr_a is NOT Teraspace-addr; then goto check_gt_cnd

   r18 = high-order 4 bits of addr_b

   // Compare r18 with the immediate value 9

   if addr_b is NOT Teraspace-addr; then goto check_gt_cnd

cmp_tera_addrs: // [4.TS] Compare two Teraspace addresses using CMPL

check_gt_cnd: r26 = 1 // [5]

   if CR3.GT is set; then goto end_stmt_16

   r26 = 0 // CR3.GT is NOT set

end_stmt_16:

   if r26 == 0, then goto stmt_18 // Not GT

stmt_17: rtn = 'G' // The GT condition is met

 

 

 

   goto stmt_26 // Branch to address stmt_26: *inlr = *on;

stmt_18: // when ptra@ < ptrb@;

 

stmt_26: // *inlr = *on;

 

Notes

[1] Load the 16-byte space pointer ptra@ into General Purpose Register (GPR) 18 and GPR 19 (r18, r19) via the IBM i-specific Load Quadwrod (LQ) instruction. The last operand (the PT field) of LQ is set to 6, which means that acceptable MI pointer types are the SLS space pointer and the Teraspace space pointer.

[1.1] If the previous LQ instruction succeeds, r25 is set to the value of r19 (the 8-byte address portion of space pointer ptra@); otherwise, r25 is set to the value zero.

[2] Load space pointer ptrb@ into r20 and r21. The 8-byte address portion of space pointer ptrb@ is copied to r22 if ptrb@ is a valid SLS or Teraspace space pointer.

[3] The CMPLA instruction compares the address portion of ptra@ (stored in r25) to the address portion of ptrb@ (stored in r22) and stores the comparison result in Condition Register (CR) field 3 (CR3). I failed to find the CMPLA instruction in public documentation of the PowerPC instruction set. I infer that CMPLA is an IBM i-specific PowerPC instruction. Experiments show that a CMPLA crfD,rA,rB instruction behaves similarly to a Compare Logical (CMPL) PowerPC instruction that does a 64-bit comparisoni.e., CMPLA crfD,1,rA,rB. It compares the contents of rA and rB as unsigned 64-bit integers and places the comparison result in CR field crfD. Bit 0, 1, or 2 of crfD is set when the comparison result is negative (LT), positive (GT), or equal (EQ), respectively. When the two 64-bit numbers stored in rA and rB are not in the same segmented 16M range (SID-000000 - SID-FFFFFF), CMPLA sets the Summary Overflow (SO) bit (bit 3i.e., the fourth bit) of CR field crfD. (The XER bits 36-39 are affected in the same manner.) In this case, CMPLA 3,25,22, if the address values stored in r25 and r22 are not in the same segmented 16M range, or in other words, r25 and r22 do not address the same SLS segment, the CMPLA instruction will set the SO bit of CR field 3 (CR3). Note that the resultant conditions (LT, GT, EQ, and SO) are mutually exclusive.

[4] The BC 7,15,0x20 instruction tests the SO bit of CR field 3 (CR3) (i.e., bit 15 of CR) and branches the execution to address 0005B4 (check-gt-cnd) if the SO bit of CR3 is not set.

[4.SO] If the SO bit of CR3 is set, addr_a and addr_b are checked for Teraspace address. If one of them is not a Teraspace address, execution will be branched to label check_gt_cnd. Since the LT, GT, EQ and SO conditions are mutually exclusive, at this time when the SO bit of CR3 is set, the GT bit of CR3 will not be set. Therefore, the following instructions will be executed sequentially and the execution will continue with the next comparison statement, statement 18 when ptra@ < ptrb@.

 

Location

Object Text

Source Statement

Pseudocode/Comments

0005B4

0005B8

0005BC

0005C0

0005C4

...  

0005DC

3B400001

418D0008

3B400000

2E3A0000

41920018

      

E29E0206

ADDI 26,0,1

BC 12,13,0X8

ADDI 26,0,0

CMPI 4,1,26,0

BC 12,18,0X18

 

LQ 20,0X200(30),6

check_gt_cnd: r26 = 1 // [5]

   if CR3.GT is set; then goto end_stmt_16

   r26 = 0 // CR3.GT is NOT set

end_stmt_16:

   if r26 == 0, then goto stmt_18 // Not GT

 

stmt_18: // when ptra@ < ptrb@;

 

[4.TS] When both addr_a and addr_b are Teraspace addresses, they are compared as unsigned 64-bit integers using the CMPL instruction. The comparison result is also stored in CR3.

[5] The value of r26 is set to 1. The BC 12,13,0X8 instruction tests the GT bit of CR3 (bit 13 of CR). If the GT bit of CR3 is set (meaning the addressability contained in ptra@ is greater than the addressability contained in ptrb@), execution is in turn branched to labels end_stmt_16, stmt_17, and finally statement 26 *inlr = *on. If the GT bit of CR3 is not set, execution will be branched to label stmt_18 to process the next comparison statement, statement 18 when ptra@ < ptrb@.

 

The logic of the RISC instructions generated for the subsequent two comparison statements (when ptra@ < ptrb@ and when ptra@ = ptrb@) in cmpla01.rpgle are similar to those generated for the when ptra@ > ptrb@ statementcomparing addr_a and addr_b using CMPLA, then checking the LT and EQ condition. Since all possible result conditions (LT, GT, EQ, and SO) of CMPLA are mutually exclusive, when addr_a and addr_b and are not in the same SLS segment, none of the LT, GT, and EQ conditions (tested in statement 16, 18, and 20) will be met. So when all of the NOT LT, NOT GT, and NOT EQ conditions are met, we can be sure that addr_a and addr_b and are not in the same SLS segment.

 

Note that the RISC instructions generated for statement 16 of cmpla01.rpgle reveals that two Teraspace addresses are always treated as "in the same space" even though they do not address the Teraspace of the same MI process.

 

If you want a more elegant and efficient way to achieve the task of cmpla01.rpgle, consider the OMI Compare Pointer for Space Addressability (CMPPSPAD) instruction, an example of which is available as cmpla06.emi.

 

Junlei Li

Junlei Li is a programmer from Tianjin, China, with 10 years of experience in software design and programming. Junlei Li began programming under i5/OS (formerly known as AS/400, iSeries) in late 2005. He is familiar with most programming languages available on i5/OS—from special-purpose languages such as OPM/ILE RPG to CL to general-purpose languages such as C, C++, Java; from strong-typed languages to script languages such as QShell and REXX. One of his favorite programming languages on i5/OS is machine interface (MI) instructions, through which one can discover some of the internal behaviors of i5/OS and some of the highlights of i5/OS in terms of operating system design.

 

Junlei Li's Web site is http://i5toolkit.sourceforge.net/, where his open-source project i5/OS Programmer's Toolkit (https://sourceforge.net/projects/i5toolkit/) is documented.

BLOG COMMENTS POWERED BY DISQUS

LATEST COMMENTS

Support MC Press Online

$

Book Reviews

Resource Center

  • SB Profound WC 5536 Have you been wondering about Node.js? Our free Node.js Webinar Series takes you from total beginner to creating a fully-functional IBM i Node.js business application. You can find Part 1 here. In Part 2 of our free Node.js Webinar Series, Brian May teaches you the different tooling options available for writing code, debugging, and using Git for version control. Brian will briefly discuss the different tools available, and demonstrate his preferred setup for Node development on IBM i or any platform. Attend this webinar to learn:

  • SB Profound WP 5539More than ever, there is a demand for IT to deliver innovation. Your IBM i has been an essential part of your business operations for years. However, your organization may struggle to maintain the current system and implement new projects. The thousands of customers we've worked with and surveyed state that expectations regarding the digital footprint and vision of the company are not aligned with the current IT environment.

  • SB HelpSystems ROBOT Generic IBM announced the E1080 servers using the latest Power10 processor in September 2021. The most powerful processor from IBM to date, Power10 is designed to handle the demands of doing business in today’s high-tech atmosphere, including running cloud applications, supporting big data, and managing AI workloads. But what does Power10 mean for your data center? In this recorded webinar, IBMers Dan Sundt and Dylan Boday join IBM Power Champion Tom Huntington for a discussion on why Power10 technology is the right strategic investment if you run IBM i, AIX, or Linux. In this action-packed hour, Tom will share trends from the IBM i and AIX user communities while Dan and Dylan dive into the tech specs for key hardware, including:

  • Magic MarkTRY the one package that solves all your document design and printing challenges on all your platforms. Produce bar code labels, electronic forms, ad hoc reports, and RFID tags – without programming! MarkMagic is the only document design and print solution that combines report writing, WYSIWYG label and forms design, and conditional printing in one integrated product. Make sure your data survives when catastrophe hits. Request your trial now!  Request Now.

  • SB HelpSystems ROBOT GenericForms of ransomware has been around for over 30 years, and with more and more organizations suffering attacks each year, it continues to endure. What has made ransomware such a durable threat and what is the best way to combat it? In order to prevent ransomware, organizations must first understand how it works.

  • SB HelpSystems ROBOT GenericIT security is a top priority for businesses around the world, but most IBM i pros don’t know where to begin—and most cybersecurity experts don’t know IBM i. In this session, Robin Tatam explores the business impact of lax IBM i security, the top vulnerabilities putting IBM i at risk, and the steps you can take to protect your organization. If you’re looking to avoid unexpected downtime or corrupted data, you don’t want to miss this session.

  • SB HelpSystems ROBOT GenericCan you trust all of your users all of the time? A typical end user receives 16 malicious emails each month, but only 17 percent of these phishing campaigns are reported to IT. Once an attack is underway, most organizations won’t discover the breach until six months later. A staggering amount of damage can occur in that time. Despite these risks, 93 percent of organizations are leaving their IBM i systems vulnerable to cybercrime. In this on-demand webinar, IBM i security experts Robin Tatam and Sandi Moore will reveal:

  • FORTRA Disaster protection is vital to every business. Yet, it often consists of patched together procedures that are prone to error. From automatic backups to data encryption to media management, Robot automates the routine (yet often complex) tasks of iSeries backup and recovery, saving you time and money and making the process safer and more reliable. Automate your backups with the Robot Backup and Recovery Solution. Key features include:

  • FORTRAManaging messages on your IBM i can be more than a full-time job if you have to do it manually. Messages need a response and resources must be monitored—often over multiple systems and across platforms. How can you be sure you won’t miss important system events? Automate your message center with the Robot Message Management Solution. Key features include:

  • FORTRAThe thought of printing, distributing, and storing iSeries reports manually may reduce you to tears. Paper and labor costs associated with report generation can spiral out of control. Mountains of paper threaten to swamp your files. Robot automates report bursting, distribution, bundling, and archiving, and offers secure, selective online report viewing. Manage your reports with the Robot Report Management Solution. Key features include:

  • FORTRAFor over 30 years, Robot has been a leader in systems management for IBM i. With batch job creation and scheduling at its core, the Robot Job Scheduling Solution reduces the opportunity for human error and helps you maintain service levels, automating even the biggest, most complex runbooks. Manage your job schedule with the Robot Job Scheduling Solution. Key features include:

  • LANSA Business users want new applications now. Market and regulatory pressures require faster application updates and delivery into production. Your IBM i developers may be approaching retirement, and you see no sure way to fill their positions with experienced developers. In addition, you may be caught between maintaining your existing applications and the uncertainty of moving to something new.

  • LANSAWhen it comes to creating your business applications, there are hundreds of coding platforms and programming languages to choose from. These options range from very complex traditional programming languages to Low-Code platforms where sometimes no traditional coding experience is needed. Download our whitepaper, The Power of Writing Code in a Low-Code Solution, and:

  • LANSASupply Chain is becoming increasingly complex and unpredictable. From raw materials for manufacturing to food supply chains, the journey from source to production to delivery to consumers is marred with inefficiencies, manual processes, shortages, recalls, counterfeits, and scandals. In this webinar, we discuss how:

  • The MC Resource Centers bring you the widest selection of white papers, trial software, and on-demand webcasts for you to choose from. >> Review the list of White Papers, Trial Software or On-Demand Webcast at the MC Press Resource Center. >> Add the items to yru Cart and complet he checkout process and submit

  • Profound Logic Have you been wondering about Node.js? Our free Node.js Webinar Series takes you from total beginner to creating a fully-functional IBM i Node.js business application.

  • SB Profound WC 5536Join us for this hour-long webcast that will explore:

  • Fortra IT managers hoping to find new IBM i talent are discovering that the pool of experienced RPG programmers and operators or administrators with intimate knowledge of the operating system and the applications that run on it is small. This begs the question: How will you manage the platform that supports such a big part of your business? This guide offers strategies and software suggestions to help you plan IT staffing and resources and smooth the transition after your AS/400 talent retires. Read on to learn: